In most cases, modern electronic system design involves designing various components or systems that are close to each other. The design and pin output of the IC are determined by the location of the circuit on the chip. Package designers use the chip design to throw off the wall ", and as far as possible package key design short wire, so that the package as small as possible. Then the PCB designer, usually has picked up the package IC, Voices of discontent., rack their brains to find wiring method for signal, and it always looks like is wrong on a pin or ball.
With the increasing complexity of the SoC and the development of multi chip packages, companies have begun to recognize the value of cross field collaboration between IC, the packaging substrate, and the PCB design group. Because of the high cost of the device and the cost sensitivity of the device, engineers have had to rethink how to plan and optimize the I/O layout of the chip while compromising on complex IC package variables. And do all of this for multiple board platforms. Now, the emergence of tools has enabled packaging and PCB design to become a collaborative and mutually beneficial process.
To make the most of it, the EDA tool should be aware of the tools that will be used in other processes. In the field of packaging and PCB design, little is known about each other. To be sure, the FPGA pin output can be defined by the user in a certain range, but the standard component does not normally have such an option.
To make tools clear, design and product design to other links in the process, these tools can cooperate in a shorter time and deliver better system design. In addition, standard IC chips can be packaged in different ways, depending on the shape parameters of the terminal products, thereby achieving a more optimized solution in various ways.
How can tools quickly recognize each other and then work together to deliver better designs? The design of smartphones and tablets using the same CPU chip can perfectly illustrate this model. Clearly, many Mobile Devices Inc are making such an attempt.
However, compared to smart phones, tablet PCs on the PCB board available area is obviously greater, and its constraints are less. As a result, CPU packages on tablets may be larger, have different pin outputs, or may be more powerful than CPU power consumption on smartphones. Therefore, a single "standard" package may not be the best application package.
Tablet designs may have more usable substrate areas, layout, CPU, and bonding circuits that enable the upper package to operate. But for smartphones using the same CPU, this approach requires too much space, so a better solution is to use lower layers.
Now, with the new tools, designers can configure the chips, look at the design from the encapsulated perspective, move to PCB (traditional methods), or first understand the PCB design requirements, and then return to the package design. In addition, they can get every product using the CPU, and then turn back from PCB to design the best package for the design optimization.
From the packaging point of view, the physical design rules are determined by the PCB design requirements. The tool then interacts with the rules and packaging designers to deliver the best package for the chip specific application. This relatively fast package design also explores different ideas to quickly find the best solution.
In general, physical shape parameters are the major constraint of product design. Using path finding tools, encapsulation and PCB designers can collaborate to find the best packages within the physical design constraints and simplify fan out and wiring in complex packages.
For each design, conventional cabling can be performed on the PCB to determine the optimum package and pin output. The rule allows designers to define various parameters, such as unused output corners, pins, differential connections, methods of assigning power and ground, and methods of processing data and address buses.
Tool cognitive design has significant advantages, and it can be optimized in any design area. First, it makes it easier to customize multiple package designs to optimally utilize a given component in accordance with the required shape parameters. Then look at the design from several "hypothetical" analysis scenarios, such as smaller packages, less cost, easiest fanout and exit. Secondly, because of the large number of pins, it is difficult to design packages by using spreadsheets and pin lists. When manual input of hundreds of pin data, the error rate is almost 100%. Of course, the advantages include improved quality, better packaging for the best shape parameters, less errors, and a lot of time in the overall system design.