Advanced circuit assembly technology in 21st Century

- Aug 30, 2016-

     Electronic components is the cell of electronic information equipment, the board level circuit assembly technology is the basis of the manufacture of electronic equipment. The emergence of different types of electronic components will lead to a revolution in the board level circuit assembly technology. In the 1960s and the integrated circuit the rise and the through-hole Technology (THT), with the vigorous development of the second half of the 70's LSI is debut in the 1980s the first generation of SMT replaced, QFP around terminal type package has become today's mainstream package; in the 1990s, with QFP HAZAMA spacing, board level assembly technology challenges, although the development of the narrow spacing assembly technology (FPT), but below 0.4mm pitch of board level circuit assembly still have many technology to solve. As the ideal solution before 90 time half period of the United States put forward the second generation of surface mount technology of IC package side array package (BGA). The closer to the small package is the chip size package (CSP) is in the 90s of the 20th century has become the focus of people's concern, such as assembly practical difficulties of more than 400 pin QFP seal by the terminal spacing can be easily assembled at 1.0-1.5 PBGA and TBGA instead, this kind of device group than the reflow. Especially in the chip and the connection of the package substrate using a flip chip connection technology, so that thousands of needles in the PCBA super computer, workstation applications, called FCBGA, is beginning to be practical. On behalf of the third assembly technology direct chip board level assembly, but due to the restriction of reliability, cost and KGD etc., only in special areas of application, the further development of the IC package, the end of 1999 budding chip package (WLP) area array projection type FC to 2014 looking forward to become a corresponding semiconductor device multi needle and high performance requirements, a representative of the third surface assembly and packaging.

     IC package has been lagging behind the ability of the IC chip itself. We want to reduce the performance gap between the bare chip and the packaged chip, which promotes the development of new design and new packaging technology. In the new package design, multi chip package (CSP) contains more than one chip, stacked on top of each other, by wire bonding and flip chip design (in flip chip line welding, welding online flip chip, or online welding on-line welding) to realize the interconnection between chip, further reducing the weight of the device and the space occupied by).

     Due to the size and cost advantages, wafer level CSP (Wafer-levelcap) of the will be further developed, this technique is in wafer is cut into small cubes (chip) before, on the chip formation of first level interconnects and packages for I / O terminal, which not only shorten the manufacturing cycle, the I / O terminal points for area array type and peripheral type (according to the distribution of the I / O terminal) of two types; the former, EIAJ terminal spacing less than 0.8mm, size and shape 4mm-21mm ultra small package, as standard. It is mainly used in logic and storage devices, and the latter is son and QFN surrounding terminals with no lead line miniaturization sealing bag. It is mainly used in the memory and low-grade logic device. Since the beginning of the 90s since the advent of CSP, the structure of all kinds, now to the array type FBGA is the mainstream, the first generation of FBGA is facing the plastic type type, the second generation of FBGA is facing down belt type, using the lead frame module, plastic package, and a new generation of FBGA is transmitted in crystal as a carrier, cutting (underlined) final assembly process, namely WLP, replaces the previous package using connection technology (wire bonding and flip chip bonding, TAB), but in line before segmentation by wiring technology of semiconductor process before, the chip pad is connected with the external terminal to complete the solder ball connections and electrical testing in wafer state, and finally forced for line segmentation. Apparently produced by WLP is the actual size of the chip FBGA, and FC no difference between the shape.

     In short, PBGA, TBGA, FBGA, (CSP) and FC is the development trend of the IC package. Table 1 and table 2 show the trends of these packages. In the first 15 years of twenty-first Century, the third representative assembly package will be developed rapidly, and the diversification of the packaging structure will be the most prominent feature of the IC package in early twenty-first Century. LSI chip stacked package, ring package: there will be a new 3D package, optical electronics interconnection, optical surface assembly technology will flourish. System on chip (SOC) and MCM system level packaging MCM/SIP with improvement of tool design, wiring density increased, new substrate materials used, and economic KGD supply of popularity, will be further developed and entered the practical stage.

     Integrated passive components are encapsulated in the following forms:

Array: many of the types of passive components are integrated together in order to face the array of terminals in the form of packaging;

Network: many hybrid resistors and capacitors are integrated together to form a peripheral terminal package;

Hybrid: hybrid integration of passive components and active components for packaging;

To embed passive components in PCB or other substrates;

Integration: the integrated passive components are encapsulated in QFP or TSOP format.

     The popularization and application of these passive packages can effectively solve the problem of the bottleneck, improve the balance of SMT production line, reduce the cost, increase the output and improve the assembly density.

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