Electronic circuits are getting smaller and smaller, and chipmakers face increasing difficulties in transistor design and manufacturing. For many years, the technical route, process equipment and production conditions of silicon based planar devices have been faced with major adjustments. The semiconductor chip along the path of smaller units area, finer line width, lower cost, lower power consumption evolution forward, different technology nodes have different technical hurdles, it will be developed to solve different techniques.
High costs are two major problems facing the two manufacturers. "Industry on the 14nm node using FinFET technology has basically become a consensus, since the technical realization has no major obstacles, the key is to find effective ways to reduce costs, otherwise there will be only a few can afford high margin products 14nm process." Wei Shaojun, a professor at the Microelectronics Institute of Tsinghua University, pointed out.
"In the last 50 years, the three elements of the chip - price, power, and performance - have always been co operating," says Mo Dakang, a semiconductor expert. In fact, purely technically, 28 or 10 nm can be achieved, but must consider the price, power consumption and performance of the three elements. Because after 28 nm, the technical complexity and manufacturing costs will be substantially improved."
According to Mo Luo's introduction: "for now, FinFET and FD, SOI two technologies each have advantages and disadvantages, are in progress, it is difficult to say who will certainly win.". Among them, FinFET technology needs to begin from IC design, build new zoology chain, the craft is complex. This affects the rate of finished products and costs. For FD SOI, its SOI silicon is costly, to $500 a piece, compared to $80 per inch of a 12 inch wafer. However, the FD SOI is still in the 2D category, and the changes in all aspects are not as great as FinFET. It is easier for manufacturers to transition, and FD SOI is especially suitable for the manufacture of high frequency or low power devices."
In short, the two technology roadmap is still in the hands of the decision makers, Intel, Qualcomm, TSMC, Samsung and other manufacturers to adopt as a decisive factor.
The key to restrict the development of China's semiconductor industry is still the lack of core technology and products which are difficult to meet the market demand. Global semiconductor into the depth adjustment period of change, both to our country's challenges, but also for the realization of "bend overtaking" provides the conditions. For the next stage of the process, what kind of layout strategy should we adopt?
Wei Shaojun believes that a careful analysis of the plane body silicon, FinFET technology and FD SOI technology in 22nm and after each process node and the advantages and disadvantages of the competition field, not blindly listen to others, because now even the world first-class enterprises were not clear about the development direction, constantly explore and adjustment. On the basis of scientific analysis and careful proof, dare to break the routine and go out of one's own way. In this regard, the strategic vision of the enterprise leaders, decision-making ability is a severe test.
Cadence president and CEO Chen Liwu believes that in the long run, the future of mainstream technology is still FinFET. Although there are some challenges in EUV in the short run, it can be overcome as long as possible. Intel, TSMC and a large number of enterprises on the industry chain have made great efforts on the FinFET, invested a lot of money, and created a more perfect ecological environment, such as the required IP and so on. These efforts are not likely to be wasted. In this respect, FD SOI is relatively weak. At the outset, FD SOI failed to be widely adopted in 28nm nodes, and an important reason was that it could not overcome the disadvantage of IP environment. The future, FD SOI can be used as a backup process, is also a catch up from behind choice, but there is still a lot of challenges.
For decades, Chinese semiconductors have followed suit. The advantage of this is that there are others experience for reference, not easy to make a mistake (which is one of the reasons Chinese IC industry rapidly development); the downside is that behind the others, want to get beyond is not easy. Now, the gap between China's semiconductor and the international advanced level is narrowing, and the strategy has become more and more inferior. The current situation in the integrated circuit industry also provides us with an opportunity to overtake corners. Will the opportunity capture the wisdom that will test Chinese semiconductor practitioners?. At the same time, there is one need to remind, "turning corners" is not only the opportunity to overtake, but also more dangerous.