China's next generation of IC technology needs careful arrangement

- Sep 20, 2017-

Electronic circuits are getting smaller and smaller, and chipmakers face increasing difficulties in transistor design and manufacturing. In 1965 1975, "Moore's law" and "Danner's law" constructed "scaled geometry" of the times in the 10 years after the nano, silicon planar devices based on the technical route, process equipment and production conditions, face a major adjustment. The international semiconductor industry has entered a period of adjustment and change, which is both an opportunity and a challenge for Chinese enterprises.

Semiconductor chips are evolving along smaller, per unit area, finer line width, lower cost, lower power paths, and different technology nodes have different technical barriers. On the 20nm node, the industry generally believes that FinFET technology is not necessary, but after the 20nm, there are two main technology roadmap: Intel and TSMC led FinFET technology, and IBM, ST led FD SOI technology. As Intel and TSMC dominate the IC manufacturing industry, the FinFET is no doubt the mainstream.

However, in recent years, the logic chip process in the evolution of 10 nm node, the pace of progress encountered headwinds. Intel originally scheduled continuation Haswell 14nm process Broadwell processor in production by the end of 2013, however, the amount of labor has been postponed to the second half of 2014, and may even be delayed until next year to meet with consumers. The development of TSMC's 16nm process has also been reported as a result of poor development.

High costs are two major problems facing the two manufacturers. "Industry on the 14nm node using FinFET technology has basically become a consensus, since the technical realization has no major obstacles, the key is to find effective ways to reduce costs, otherwise there will be only a few can afford high margin products 14nm process." Wei Shaojun, a professor at the Microelectronics Institute of Tsinghua University, pointed out.

The lack of lithography power in EUV lithography is the main reason for the high cost of FinFET technology under 10nm and 10nm. Lam Research academicians Reza Arghavani pointed out that, for semiconductor manufacturing, EUV can not be imported in time, the industry can also use spacer graphical technology to achieve. But the problem is that the spacer process requires three masks to achieve results, which results in a significant increase in manufacturing costs and time. So without EUV, the patterning of lithography in the future is a problem.

"In the last 50 years, the three elements of the chip - price, power, and performance - have always been co operating," says Mo Dakang, a semiconductor expert. In fact, purely technically, 28 or 10 nm can be achieved, but must consider the price, power consumption and performance of the three elements. Because after 28 nm, the technical complexity and manufacturing costs will be substantially improved."

In short, the two technology roadmap is still in the hands of the decision makers, Intel, Qualcomm, TSMC, Samsung and other manufacturers to adopt as a decisive factor.

The key to restrict the development of China's semiconductor industry is still the lack of core technology and products which are difficult to meet the market demand. Global semiconductor into the depth adjustment period of change, both to our country's challenges, but also for the realization of "bend overtaking" provides the conditions. For the next stage of the process, what kind of layout strategy should we adopt?

Cadence president and CEO Chen Liwu believes that in the long run, the future of mainstream technology is still FinFET. Although there are some challenges in EUV in the short run, it can be overcome as long as possible. Intel, TSMC and a large number of enterprises on the industry chain have made great efforts on the FinFET, invested a lot of money, and created a more perfect ecological environment, such as the required IP and so on. These efforts are not likely to be wasted. In this respect, FD SOI is relatively weak. At the outset, FD SOI failed to be widely adopted in 28nm nodes, and an important reason was that it could not overcome the disadvantage of IP environment. The future, FD SOI can be used as a backup process, is also a catch up from behind choice, but there is still a lot of challenges.

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