We often find that some of the rules or arguments we take for granted tend to make mistakes. Electronic engineers will also have such examples in circuit design. Here is a summary of eight misunderstandings that an engineer has summed up.
Misunderstanding 1: this board PCB design requirements are not high, with a little bit of line, automatic cloth
Comment: automatic wiring must occupy the PCB larger than the manual wiring, also produced many times through holes, in large batch products, manufacturers are considering factors of PCB price in addition to business factors, is the line width and the number of vias, which affect the amount of goods and the consumption of PCB bit rate, saving the cost of the supplier, and also to find a reason for price.
Error two: these bus signals are pulled with a resistor, feel relieved
Comment: there are many reasons why the signal needs to be pulled down, but not everyone has to pull it. On the pull down resistor is a simple input signal, the current will be tens of microamperes, but pull a driven by the signal, the current will reach the Ma level, now the system is often the 32 bits of the address data, there may be 244/245 bus isolation and other signals are pulling, power consumption a few Watts is consumption in these resistance.
Myth three: how do you deal with these I/O CPU and FPGA? Let it be empty, then
Comments: do not use the I/O port, if left vacant, a little interference by the outside world, it may become repeated oscillation of the input signal, and the power consumption of the MOS device basically depends on the number of turns of the gate circuit. If it is pulled up, each pin will also have a current of 1, so the best way is to set the output (of course, the outside can not be connected to other driving signals)
Misunderstanding four: this FPGA still has so many doors, you can use it
Comment: the power consumption of FGPA is proportional to the number of flip flops used and the number of flip flops, so the power consumption of the same model FPGA may differ by 100 times in different circuits and at different times. Minimizing the number of flip flops at high speed is the fundamental way to reduce FPGA power consumption.
Error five: the power consumption of these small chips are very low, without consideration
Comments: not too complex for the internal power consumption of the chip is very difficult to determine, which is mainly composed of a current pin on the determination of a ABT16244, if no load power is probably less than 1 mA, but its index is the load of each foot can drive 60 MA (electric resistance, such as tens of ohms), i.e. the maximum power up to 60*16=960mA full load, of course, only the power of such a large current, heat load to me.
Misunderstanding six: there are so many memory control signals, I only need the board with the OE and WE signals can be, chip select grounding, so read data out much faster
Comments: the most effective memory power in CS (irrespective of OE and WE) will be 100 times larger than the chip select is invalid, so it should be possible to use CS to control chip, and meet other requirements of the situation as soon as possible to choose short pulse width reduction.
Myth seven: How have all these signals been rushed? As long as the match is good, it can be eliminated
Comments: in addition to a small number of specific signals (such as 100BASE-T, CML), have been flush, as long as it is not very large, do not necessarily need to match, even if the match is not to match the best. As the output impedance of the TTL is less than 50 ohm, 20 ohm or even if, also with such big, resistance, the current is very large, the power consumption is unacceptable, the signal amplitude will also too small, and the general signal at the output impedance of the output high level and low level of output is not the same, there is no way to completely match. Therefore, the TTL, LVDS, 422 and other signals matching, as long as the overshoot can be accepted.
Error eight: reducing power consumption is a matter of hardware personnel, and software does not matter
Comment: the hardware is only set up a stage, singing is a software bus almost every chip access, each signal flip almost all controlled by software, if the software can reduce the memory access times (use register variables and the use of internal CACHE etc.), timely response to interrupt (interrupt is often active low and with a pull-up resistor) and other specific for single board specific measures will make a great contribution to reduce power consumption.