There are many ways to solve the EMI problem. Modern EMI suppression methods include the use of EMI to suppress the coating, the selection of appropriate EMI suppression parts and EMI simulation design. This article from the most basic PCB layout of PCB layered discussion in the control of EMI radiation and the role of design skills.
The reasonable capacity of capacitance in the vicinity of the power pin of the IC can make the IC output voltage jump faster. However, the problem is not so far. Because the capacitance is characteristic of a finite frequency response, this makes the capacitor unable to generate the harmonic power required to drive the IC output clean in the full band. Besides, the transient voltage formed on the power supply bus will cause voltage drops at the ends of the decoupled path, which are the main common mode EMI interference sources. How should we solve these problems?
In order to control the common mode EMI, the power supply layer helps to decouple and have enough low inductance. The power supply layer must be a matched pair of power supply with fairly good design. Some people may ask, "to what extent is it right? The answer depends on the power stratification, the material between layers and the frequency of operation (i.e. the function of IC rise time). Generally, the spacing between the layers of the power supply is 6mil, the interlayer is the FR4 material, and the equivalent capacitance of the power layer per square inch is about 75pF. Obviously, the smaller the spacing is, the larger the capacitance is.
From the signal line, a good stratification strategy should be to put all the signal lines on one or more layers, which are close to the power layer or the ground. For power supply, a good layering strategy should be the power supply layer adjacent to the ground layer, and the distance between the power supply layer and the ground layer is as small as possible, which is what we call the "layering" strategy.
There are some potential problems in the design of 4 laminate. First, the traditional four laminate with a thickness of 62mil, even if the signal layer is in the outer layer, the power supply and the grounding layer are in the inner layer, and the distance between the power layer and the ground is still too large.
If the cost requirements are first, the following two traditional 4 laminate alternatives can be considered. These two schemes can improve the performance of EMI suppression, but they are only suitable for boards with low density and enough area around the components (placing the required power supply copper clad layer).
The first is the first choice, the outer layer of PCB is the formation, and the two layers in the middle are all signal / power layer. The power supply on the signal layer uses a wide line, which makes the path impedance of the power current low and the impedance of the signal microstrip path is low. From the point of view of the EMI control, this is the best 4 layer PCB structure available. The outer layer of the second scheme takes the power and the ground, and the middle two layers signal. Compared to the traditional 4 laminate, the scheme is less improved, and the interlayer impedance is as bad as the traditional 4 laminate.
If you want to control the line impedance, the stack would have to carefully pick the floor will take the line layout in power and the bottom of copper island. In addition, the copper paving islands in the power or stratum should be interconnected as much as possible to ensure the connectivity of DC and low frequency.
General high performance 6 laminate design generally uses first and sixth layers for formation, third and fourth layers to power and ground. The EMI suppression ability is excellent because of the double microstrip signal line between the two layers in the power layer and the ground layer. The drawback of the design is that the line layer is only two layers. As described earlier, the same stack can be achieved with the traditional 6 laminate if the outer line is short and copper is laid in the non - walk line area.
Because the insulation isolation layer between layers is very thin, the impedance between 10 or 12 layers of circuit board layer is very low. As long as there is no problem in layering and stacking, it is desirable to get excellent signal integrity. It is difficult to manufacture 12 laminate according to the thickness of 62mil, and there are not many manufacturers that can process 12 laminate.
This design provides a good path for the signal current and its circuit current. The appropriate wiring strategy is that the first layer walks along the X direction, the third layer walks along the Y direction, the fourth layer walks along the X direction, and so on. Intuitively look at the running line. The first level, the 1 and the third tier are a pair of stratified combinations. The fourth level and the seventh tier are a pair of stratified combinations, the eighth and tenth layers are the last pair of stratified combinations. When there is a need to change the direction of the line, the signal line on the first layer should change the direction from the "hole" to the third layer. In fact, it may not always be done, but as a design concept, we should keep it as much as possible.
Similarly, when the direction of the signal changes the direction of the line, it should be through the holes from the eighth and tenth layers or from the fourth to the seventh. This wiring can ensure that the coupling between the forward path and the loop of the signal is most tight. For example, if the signal line in the first layer, second layer and only in the loop on the second floor walk the line, then the signal on the first even by the "hole" to the third layer, the loop is still in the second layer, so as to maintain the characteristics of low inductance, capacitance and good electromagnetic shielding performance.