Through the analysis of the parasitic characteristics of vias, we can see that in the high-speed PCB design, the seemingly simple vias often have a lot of negative effects on the circuit design. In order to reduce the adverse effects of parasitic effects through vias, the design can be done as much as possible:
1, from the cost and signal quality of two considerations, select a reasonable size of the hole size. For example, the 6-10 layer memory module PCB design, the use of 10/20Mil (drilling / pad) through the hole is better, for some high-density small size of the board, you can also try to use the 8/18Mil through the hole. At present, it is difficult to use smaller size vias under technical conditions. For power or ground vias, a larger size may be considered to minimize impedance.
2, the two formulas discussed above can be used to reduce the two parasitic parameters of vias by using thinner PCB plates.
3, PCB signal on the board as far as possible without changing the layer, that is to say, do not use unnecessary vias.
4, the power and ground pins to the nearest hole, the hole and the pin between the shorter the better, because they will lead to an increase in inductance. At the same time, the power and ground lead should be as thick as possible to reduce the impedance.
5. Some ground vias are placed near the vias of the signal transfer layer to provide the closest loop for the signal. You can even place a number of redundant ground vias on the PCB board. Of course, flexibility is needed in design. The cross hole model discussed above is a pad for each layer, and sometimes we can reduce or even remove some layers of pads. Especially in the hole density is very large, may lead to a broken circuit partition groove is formed on a copper layer, to solve this problem in addition to move the position of the hole, we can also consider a decrease in the size of the hole pad copper layer.