FPGA (Field-Programmable Gate Array), that is, field programmable gate array, which is based on PAL, GAL, CPLD and other programmable devices on the basis of further development of the product. It is used as a semi custom circuit in the field of special integrated circuit (ASIC), which not only solves the shortcomings of the custom circuit, but also overcomes the shortcomings of the original programmable devices.
FPGA working principle
FPGA uses a logic cell array LCA (Logic Cell Array) of such a concept, including the internal configurable logic module CLB (Configurable Logic Block), IOB (Input Output input and output module Block) and internal connections (Interconnect) three parts. Field programmable gate array (FPGA) is a programmable device. With the traditional logic circuit and gate array (such as PAL, GAL and CPLD devices) compared FPGA with different structures, FPGA using small lookup tables (16 * 1RAM) to realize the combination of logic, each lookup table is connected to the input terminal of a D trigger, the trigger and drive other logic circuits or drive I/O, which the basic logic unit module can realize the combination of logic function and can realize sequential logic functions, these modules are connected to each other or connected to the I/O module using metal wire. The logic of FPGA is achieved by loading to the internal static memory cell programming data, the values stored in the memory unit determines the connection between logic function logic unit and each module or modules with I/O, and the final decision of the FPGA can realize the function, FPGA allows unlimited programming.
1) using FPGA design ASIC circuit (ASIC), the user does not need to cast production, you can get a practical chip.
2) FPGA can be used in other fully custom or semi custom ASIC circuit in the sample piece.
3) the FPGA has rich internal triggers and I/O pins.
4 (ASIC) FPGA is one of the most common devices in the design cycle, the lowest cost and the least risk.
5) FPGA adopts high speed CMOS technology, low power consumption, can be compatible with CMOS, TTL level.
It can be said that the FPGA chip is one of the best choices to improve system integration and reliability in small batch systems.
FPGA is stored in the on-chip RAM program to set its working state, therefore, the need to work on the on-chip RAM programming. Users can use different programming modes according to different configuration mode.
Power up, the FPGA chip will read the data into the EPROM chip RAM programming, configuration is completed, the FPGA into the working state. After power down, FPGA restored into white, the internal logic relationship disappeared, so FPGA can be used repeatedly. FPGA programming does not require a dedicated FPGA programmer, just use the generic EPROM, PROM programmer can. When you need to modify the FPGA function, just a piece of EPROM can be. In this way, the same piece of FPGA, different programming data, can produce different circuit functions. Therefore, the use of FPGA is very flexible.
FPGA configuration mode
FPGA has a variety of configuration modes: parallel main mode for a FPGA and a EPROM; a master-slave mode can support a plurality of FPGA PROM programming; serial mode can use serial programming PROM FPGA; peripheral mode can be FPGA as the microprocessor peripherals, a microprocessor for its programming.
How to achieve fast timing convergence, reduce power consumption and cost, the optimization of clock management and reduce FPGA and PCB concurrent design complexity, is always the key problem of system design engineers need to consider using FPGA. Now, with the development of FPGA to a higher density, larger capacity, lower power consumption and more integrated in the direction of IP, system design engineer in benefit from these excellent performance at the same time, have to face new challenges due to FPGA hitherto unknown performance and ability level.
For example, the leading FPGA vendor Xilinx recently introduced the Virtex-5 series using the 65nm process, which can provide up to 330 thousand logic units, 1200 I/O and a large number of hard IP blocks. The large capacity and density make the complex wiring more unpredictable, which leads to more serious problem of time series convergence. In addition, a number of logic functions, DSP, embedded processing and interface modules, which are integrated for different applications, make clock management and voltage allocation problems more difficult.
Fortunately, FPGA vendors, EDA tool vendors are working together to solve the unique design challenges of 65nm FPGA. Not long ago, Synplicity and Xilinx announced the establishment of a joint working group of super capacity timing convergence, designed to help the system design engineers to maximize the use of 65nm FPGA devices in a faster and more efficient manner. Magma, an integrated tool designed by FPGA, a software vendor, can help build an optimized layout and speed up the convergence of Blast.